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Analysis of institutional authors

Vázquez DAuthorRodriguez AAuthorOtero AAuthorDe La Torre EAuthor

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January 9, 2023
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Proceedings Paper
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Extending RISC-V Processor Datapaths with Multi-Grain Reconfigurable Overlays

Publicated to:Dcis 2022 - Proceedings Of The 37th Conference On Design Of Circuits And Integrated Systems. 137-142 - 2022-01-01 (), DOI: 10.1109/DCIS55711.2022.9970069

Authors: Vázquez, D; Rodríguez, A; Otero, A; de la Torre, E

Affiliations

Centro de Electronica Industrial - Author
Univ Politecn Madrid, Ctr Elect Ind, Madrid, Spain - Author

Abstract

The use of accelerators to perform computing offloading from software to hardware in heterogeneous computing systems has already been around for some time. The most common approach is to have hardware accelerators loosely-coupled with the main processor of the system to allow parallel execution. However, this can negatively affect performance in certain application scenarios. A different approach, which is gaining momentum nowadays thanks to the mainstream adoption of RISC-V, is to create accelerators that combine a processor core with dedicated and tightly-coupled hardware modules that are transparently managed via custom ISA extensions. These modules, which are often application-specific, become part of the processor datapath and cannot be changed after deployment. In this paper, a novel reconfigurable RISC-V processor is presented. Its datapath has been modified to include a spatially-configured CGRA overlay that is accessible through custom ISA extensions. The functionality of the overlay can be adapted at run time through reconfiguration. The proposed architecture is accompanied by a toolchain capable of automatically transforming loop-based computing-intensive sections of the application code into configuration data controlling the operations executed in the overlay. Experimental results show a performance improvement of up to 13x compared to alternative software-based and memory-mapped hardware-based implementations.

Keywords

fpga overlayshardware accelerationrun-time reconfigurationCodesComputer architectureFpga overlaysHardware accelerationHeterogeneous networksIntegrated circuitsRisc-vRun-time reconfigurationSoftware

Quality index

Bibliometric impact. Analysis of the contribution and dissemination channel

From a relative perspective, and based on the normalized impact indicator calculated from the Field Citation Ratio (FCR) of the Dimensions source, it yields a value of: 1.32, which indicates that, compared to works in the same discipline and in the same year of publication, it ranks as a work cited above average. (source consulted: Dimensions Jul 2025)

Specifically, and according to different indexing agencies, this work has accumulated citations as of 2025-07-20, the following number of citations:

  • Scopus: 3

Impact and social visibility

From the perspective of influence or social adoption, and based on metrics associated with mentions and interactions provided by agencies specializing in calculating the so-called "Alternative or Social Metrics," we can highlight as of 2025-07-20:

  • The use of this contribution in bookmarks, code forks, additions to favorite lists for recurrent reading, as well as general views, indicates that someone is using the publication as a basis for their current work. This may be a notable indicator of future more formal and academic citations. This claim is supported by the result of the "Capture" indicator, which yields a total of: 7 (PlumX).

Leadership analysis of institutional authors

There is a significant leadership presence as some of the institution’s authors appear as the first or last signer, detailed as follows: First Author (VAZQUEZ IGLESIAS, DANIEL) and Last Author (TORRE ARNANZ, EDUARDO DE LA).