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This work was supported by the Spanish Ministry of Economy and Competitiveness under the project PLATINO, with reference number TEC2017-86722-C4-2-R
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Ortiz, AlbertoAutor o CoautorRodriguez, AlfonsoAutor o CoautorOtero, AndresAutor o CoautorDe La Torre, EduardoAutor o CoautorData Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems
Publicado en:2019 14th International Symposium On Reconfigurable Communication-Centric Systems-On-Chip (Recosoc 2019). 20-26 - 2019-01-01 (), DOI: 10.1109/ReCoSoC48741.2019.9034940
Autores: Ortiz, Alberto; Rodriguez, Alfonso; Otero, Andres; de la Torre, Eduardo;
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Resumen
The use of accelerator-centric processing architectures in different application scenarios, ranging from the cloud to the edge, is nowadays a reality. However, the always increasing stringent operating conditions and requirements continues to push the research around hardware-based processing architectures, which are able to provide medium to high computing performance capabilities while at the same time supporting energy-efficient execution. In addition, reconfigurable devices (i.e., FPGAs) provide another degree of freedom by enabling software-like flexibility by time-multiplexing the computing resources. Nevertheless, bus-based computing platforms still face architectural bottlenecks when data transfers are not handled efficiently. In this paper, the communication overhead in a re configurable multi-accelerator architecture for high-performance embedded computing is analyzed and modeled. The obtained models are then used to predict the acceleration perfomance and to evaluate two different patterns for data transfers: on the one hand, a basic approach in which data preparation and DMA transfers are executed sequentially; on the other hand, a pipelined approach in which data preparation and DMA transfers are executed in parallel. The evaluation method is based on well-known accelerator benchmarks from the MachSuite suite. Experimental results show that using a pipelined data management approach increases performance up to 2.6x when compared to the sequential alternative, and up to 26.46x when compared with a bare-metal execution of the accelerators (i.e., without using the reconfigurable multi-accelerator processing architecture nor an Operating System).
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2025-07-21:
- WoS: 1
- Scopus: 1
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Existe un liderazgo significativo ya que algunos de los autores pertenecientes a la institución aparecen como primer o último firmante, se puede apreciar en el detalle: Primer Autor (ORTIZ CUADRADO, ALBERTO) y Último Autor (TORRE ARNANZ, EDUARDO DE LA).