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This work was partially supported by the Spanish Ministry of Economy and Competitiveness under the project REBECCA (Reference TEC2014-58036-C4-2-R), and the FPI grant program of said Ministry (Grant No. BES-2012-060459). The LUT-based PEs were originally developed in collaboration with Ing. Roland Dobai, Ph.D., from Brno University of Technology.

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On the scalability of evolvable hardware architectures: comparison of systolic array and Cartesian genetic programming

Publicat a:Genetic Programming And Evolvable Machines. 20 (2): 155-186 - 2019-06-01 20(2), DOI: 10.1007/s10710-018-9340-5

Autors: Mora, Javier; Salvador, Ruben; de la Torre, Eduardo;

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Resum

Evolvable hardware allows the generation ofcircuits that areadapted to specific problems by using an evolutionary algorithm (EA). Dynamic partial reconfiguration of FPGA LUTs allows making the processing elements (PEs) of these circuits small and compact, thus allowing large scale circuits to be implemented in a small FPGA area. This facilitates the use of these techniques in embedded systems with limited resources. The improvement on resource-efficient implementation techniques has allowed increasing the size of processing architectures from a few PEs to several hundreds. However, these large sizes pose new challenges for the EA and the architecture, which may not be able to take full advantage of the computing capabilities of its PEs. In this article, two different topologiessystolic array (SA) and Cartesian genetic programming (CGP)are scaled from small to large sizes and analyzed, comparing their behavior and efficiency at different sizes. Additionally, improvements on SA connectivity are studied. Experimental results show that, in general, SA is considerably more resource-efficient than CGP, needing up to 60% fewer FPGA resources (LUTs) for a solution with similar performance, since the LUT usage per PE is 5 times smaller. Specifically, 10 x 10 SA has better performance than 5 x 10 CGP, but uses 50% fewer resources.

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